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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>FMAX (scalar) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">FMAX (scalar)</h2>
      <p class="aml">Floating-point Maximum (scalar). This instruction compares the two source SIMD&amp;FP registers, and writes the larger of the two floating-point values to the destination SIMD&amp;FP register.</p>
      <p class="aml">When <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>.AH is 0, the behavior is as follows:</p>
      <ul>
        <li>Negative zero compares less than positive zero.</li>
        <li>When <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>.DN is 0, if either value is a NaN, the result is a quiet NaN.</li>
        <li>When <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>.DN is 1, if either value is a NaN, the result is Default NaN.</li>
      </ul>
      <p class="aml">When <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>.AH is 1, the behavior is as follows:</p>
      <ul>
        <li>If both values are zeros, regardless of the sign of either zero, the result is the second value.</li>
        <li>If either value is a NaN, regardless of the value of <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>.DN, the result is the second value.</li>
      </ul>
      <p class="aml">This instruction can generate a floating-point exception. Depending on the settings in <a class="armarm-xref" title="Reference to Armv8 ARM section">FPCR</a>, the exception results in either a flag being set in <a class="armarm-xref" title="Reference to Armv8 ARM section">FPSR</a>, or a synchronous exception being generated. For more information, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Floating-point exception traps</a>.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td colspan="2" class="lr">ftype</td><td class="lr">1</td><td colspan="5" class="lr">Rm</td><td class="l">0</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td class="r">0</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td/><td/><td colspan="5"/><td colspan="2"/><td/><td colspan="5"/><td colspan="2"/><td colspan="2" class="droppedname">op</td><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">Half-precision<span class="bitdiff"> (ftype == 11)</span><span style="font-size:smaller;"><br/>(FEAT_FP16)
            </span></h4><a id="FMAX_H_floatdp2"/><p class="asm-code">FMAX  <a href="#sa_hd" title="16-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Hd&gt;</a>, <a href="#sa_hn" title="First 16-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Hn&gt;</a>, <a href="#sa_hm" title="Second 16-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Hm&gt;</a></p></div><div class="encoding"><h4 class="encoding">Single-precision<span class="bitdiff"> (ftype == 00)</span></h4><a id="FMAX_S_floatdp2"/><p class="asm-code">FMAX  <a href="#sa_sd" title="32-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Sd&gt;</a>, <a href="#sa_sn" title="First 32-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Sn&gt;</a>, <a href="#sa_sm" title="Second 32-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Sm&gt;</a></p></div><div class="encoding"><h4 class="encoding">Double-precision<span class="bitdiff"> (ftype == 01)</span></h4><a id="FMAX_D_floatdp2"/><p class="asm-code">FMAX  <a href="#sa_dd" title="64-bit SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Dd&gt;</a>, <a href="#sa_dn" title="First 64-bit SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Dn&gt;</a>, <a href="#sa_dm" title="Second 64-bit SIMD&amp;FP source register (field &quot;Rm&quot;)">&lt;Dm&gt;</a></p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);

integer esize;
case ftype of
    when '00' esize = 32;
    when '01' esize = 64;
    when '10' UNDEFINED;
    when '11'
        if <a href="shared_pseudocode.html#impl-shared.HaveFP16Ext.0" title="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then
            esize = 16;
        else
            UNDEFINED;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Dd&gt;</td><td><a id="sa_dd"/>
        
          <p class="aml">Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Dn&gt;</td><td><a id="sa_dn"/>
        
          <p class="aml">Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Dm&gt;</td><td><a id="sa_dm"/>
        
          <p class="aml">Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Hd&gt;</td><td><a id="sa_hd"/>
        
          <p class="aml">Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Hn&gt;</td><td><a id="sa_hn"/>
        
          <p class="aml">Is the 16-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Hm&gt;</td><td><a id="sa_hm"/>
        
          <p class="aml">Is the 16-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Sd&gt;</td><td><a id="sa_sd"/>
        
          <p class="aml">Is the 32-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Sn&gt;</td><td><a id="sa_sn"/>
        
          <p class="aml">Is the 32-bit name of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Sm&gt;</td><td><a id="sa_sm"/>
        
          <p class="aml">Is the 32-bit name of the second SIMD&amp;FP source register, encoded in the "Rm" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPEnabled64.0" title="function: CheckFPEnabled64()">CheckFPEnabled64</a>();
bits(esize) operand1 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, esize];
bits(esize) operand2 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[m, esize];

<a href="shared_pseudocode.html#FPCRType" title="type FPCRType">FPCRType</a> fpcr = FPCR[];
boolean merge = <a href="shared_pseudocode.html#impl-shared.IsMerging.1" title="function: boolean IsMerging(FPCRType fpcr)">IsMerging</a>(fpcr);
bits(128) result = if merge then <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(128);

<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, 0, esize] = <a href="shared_pseudocode.html#impl-shared.FPMax.3" title="function: bits(N) FPMax(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMax</a>(operand1, operand2, fpcr);
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
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